1. Field
Exemplary embodiments of the present disclosure relate to a memory controller and an operating method thereof.
2. Description of the Related Art
Semiconductor memory devices are generally classified into volatile memory devices, such as a dynamic random access memory (DRAM) and a static RAM (SRAM), and nonvolatile memory devices, such as a read only memory (ROM), a mask ROM (MROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically EPROM (EEPROM), a ferromagnetic RAM (FRAM), a phase change RAM (PRAM), a magnetoresistive RAM (MRAM), a resistive RAM (RRAM) and a flash memory.
Volatile memory devices lose their stored data when their power supply is interrupted, whereas nonvolatile memory devices retain their data even without a constant source of power. Flash memory devices are widely used as a storage medium in computer systems because of their high program speed, low power consumption and large data storage capacity.
In nonvolatile memory devices, especially in flash memory devices, data states storable in each memory cell are determined based on the number of bits stored in the memory cell. A memory cell storing 1-bit data per cell is called a single-bit cell or a single-level cell (SLC). A memory cell storing multiple bits of data (i.e., 2 or more bits data) per cell is called a multi-bit cell, a multi-level cell (MLC) or a multi-state cell. The multi-bit cell is advantageous because it allows more data to be stored in a limited area. However, as the number of bits programmed in each memory cell increases, the reliability decreases and the read failure rate increases. What is therefore required is a scheme for precisely determining optimal read voltages for data stored in memory cells of a semiconductor memory device.